Future development in the semiconductor industry focuses on increasing the speed of and decreasing the size of integrated circuits. The requirements for speed and miniaturization are met by increasing the density of elements in those integrated circuits. These two requirements have thus become major goals in designing and manufacturing efforts concerned with MOSFETs and other semiconductor devices, including both volatile and non-volatile memory devices.
MOSFETs are metal-on-silicon field effect transistors composed of source and drain regions separated by a gate consisting of gate oxide overlaid with gate metal. Application of a voltage to the gate metal causes the formation of an electrical field underneath the gate metal which forms an electrically conductive channel in the semiconductor material underneath the gate, permitting the flow of current through the channel from the source to the drain region.
Increasing the density of elements in integrated circuits means that smaller channel lengths and widths must be used. As the dimensions of semiconductor devices decreases, the existing "long-channel" performance models for MOSFET devices predicted that a decrease in the channel length, L, or in the gate oxide thickness T.sub.ox, would increase the saturation current, I.sub.DSAT. However, as MOSFET devices were scaled below approximately 2 .mu.m, effects not predicted by the long channel models were observed and were thereafter termed "short-channel" effects.
As device dimensions of MOSFETs continued to decrease, it became apparent that problems associated with the short-channel effects could be placed in two general categories: (1) the problem of increased leakage current when the MOSFET is off, and (2) reliability problems associated with short-channel and thin gate oxide device structures.
Some of the reliability problems that arise in short-channel and thin gate oxide MOSFETs include: (1) thin gate oxide breakdown, (2) device degradation due to hot-carrier effects, and (3) reliability problems associated with interconnects between MOSFETS. One of the major problems associated with semiconductor devices other than MOSFETs involves high-temperature data retention in nonvolatile memory cells. The two problems that are of particular interest are device degradation due to hot-carrier effects and high temperature data retention problems in nonvolatile memory cells.
The characteristics of the Si--SiO.sub.2 interface determine to a great extent, the functioning of the gate dielectric. A study of the structure of the interface has resulted in the development of the concept of "surface states" and interface trapped charge, which affect the threshold voltage of MOSFET devices.
The term "surface states" refers to electronic energy states that arise in a crystal if the crystal lattice is terminated at a surface such as that existing at the Si--SiO.sub.2 interface. A theory which may account for surface states is the postulated existence of "dangling bonds." Dangling bonds are locations at which atoms do not have adjacent atoms to share available bonds. These surface states are confined to the region adjacent to the surface or to the interface. According to this theory, each of the surface states is associated with a single atom at the surface or the interface, and therefore, an electron occupying one of the surface states is considered to be localized because the electron is forced to remain in a restricted region of space centered around the atom. Because such surface states effectively trap free carriers at the surface or at the interface, they are also called "interface traps." Although the electrical behavior of the interface traps can be predicted, the physical origin of the surface states is not known exactly.
In an ideal Si--SiO.sub.2 interface, all of the Si bonds at the interface can be used for the formation of SiO.sub.2. However, this ideal state is never attained in reality, and if only a small number of these Si bonds are not used for forming SiO.sub.2, a significant number of surface states can exist. This is because, on a silicon surface, there are as many as 6.8.times.10.sup.14 Si atoms per cm.sup.2. If, for example, there are 1/1000 of these bonds left dangling, the density of charges trapped at the interface is approximately 6.8.times.10.sup.11 /cm.sup.2. With a gate oxide thickness of 20 nanometers (nm), this number of dangling bonds can cause a threshold voltage to shift by approximately 0.63 volts. This example indicates that if the dangling bond theory is correct, a relatively small number of residual dangling bonds can significantly perturb the device characteristics. These dangling bonds can be created by injection of energetic carriers, also called hot carriers, into the gate oxide.
The hot-carrier effects are of increasing importance when MOSFETS are scaled into the submicron range. The hot carrier effects are increased when the MOSFET device dimensions are reduced and the supply voltage remains constant or is not reduced in proportion to the reduction in the device dimensions. As a result of increased current density, the lateral electric field density in the channel increases, which causes the inversion-layer charges to be accelerated (or heated) to an extent that they cause a number of harmful device phenomena. The most important of these hot-carrier effects is the damage inflicted to the gate oxide and the Si--SiO.sub.2 interface. This leads to a time-dependent degradation of various MOSFET characteristics, including increased threshold voltage, decreased linear region transconductance, and decreased saturation current.
Thus, the lifetimes of conventional MOSFET structures subjected to such degradation may be reduced below the generally accepted benchmark of 10 years. This degradation has been observed in NMOS devices with channel lengths smaller than 1.5 .mu.m, and in PMOS devices with submicron channel lengths. Because of the hot-carrier effects, it is imperative to develop techniques to counteract this problem.
One of the approaches to reducing hot-carrier effects is to attempt to hydrogenate dangling bonds by annealing in hydrogen environment at approximately 400.degree. C. This is normally the last step prior to assembly and packaging of integrated circuits. This hydrogen annealing step is done to permit hydrogen to penetrate into the gate oxide and bond with the Si--SiO.sub.2 at the interface, thus forming Si--OH bonds.
However, the Si--H or Si--OH bonds can be easily broken by electrons injected as a result of hot-carrier phenomena, giving rise to free hydrogen ions, which diffuse throughout the interface and cause increased bond-breaking behavior rather than enhancing the stability of the dangling bonds.
Moreover, there are problems with high-temperature data retention in nonvolatile memory cell arrays such as EPROMs, FLASH EPROMs, and E.sup.2 PROMs. This poor high-temperature data retention may be due to mobile hydrogen atoms that diffuse to the floating gate in a nonvolatile memory cell and cause the charge on the floating gate to be lost.
One measure of date retention is the charge loss (.DELTA.VTE) measured after baking the devices at 250.degree. C. for 24 hours. The typical standard for the maximum acceptable charge loss is 0.1 V over 24 hours.
The reduced memory cell size and high-performance logic circuits has necessitated the use of a borderless local interconnect structure and trench isolation. The prior art developed a low-temperature, damascene-tungsten local interconnect for a 0.25 .mu.m channel CMOS technology with trench isolation. Once such prior art structure is described in "A Low-Temperature Local Interconnect Process in a 0.25 .mu.m-channel CMOS Logic Technology with Shallow Trench Isolation" by J. Givens et al, VMIC Conference 103:43-48 (1994). Other applications of nitride and oxynitride layers are as barrier or etch stop layers, even when local interconnects are not present.
However, the prior art includes the use of silicon nitride films that have high hydrogen content as etch stop layers. The high hydrogen content causes problems discussed in the article "Effects of Silicon Nitride Encapsulation on MOS Device Stability" by R. C. Sun et al, IEEE 80:244-251 (1980). This article describes a new threshold instability phenomenon observed in MOS transistors encapsulated with plasma deposited silicon nitride films and describes a series of experiments which indicated that the instability was due to a chemical effect associated with hydrogen in the silicon nitride film. The article postulated that the formation of surface states and fixed charges in the channel region was due to the interaction of hot carriers with hydrogen present at the interface and was the basic mechanism causing the instability.
One attempted solution to this problem is the use of low pressure (LP) CVD to deposit etch stop layers. The temperature of this process can be high, in the range of 800.degree. C. Although this high temperature removes free hydrogen from the nitride layers, LPCVD places large stresses on the film layer, making it susceptible to cracking.
Therefore, what is needed are low residual stress semiconductor devices that have low amounts of free hydrogen and methods of manufacturing such low residual stress, low hydrogen content semiconductor devices.